US 12,261,126 B2
Semiconductor package
Tsung-Hsien Chiang, Hsinchu (TW); Hsien-Ming Tu, Hsinchu County (TW); Hao-Yi Tsai, Hsinchu (TW); and Tin-Hao Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 24, 2024, as Appl. No. 18/420,767.
Application 17/460,284 is a division of application No. 16/285,216, filed on Feb. 26, 2019, granted, now 11,107,772, issued on Aug. 31, 2021.
Application 18/420,767 is a continuation of application No. 17/460,284, filed on Aug. 29, 2021, granted, now 11,923,318.
Prior Publication US 2024/0170414 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/544 (2006.01); B23K 26/352 (2014.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); B23K 101/40 (2006.01)
CPC H01L 23/544 (2013.01) [B23K 26/352 (2015.10); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 23/562 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); B23K 2101/40 (2018.08); H01L 2223/54406 (2013.01); H01L 2224/214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an encapsulated semiconductor device comprising an encapsulating material and a semiconductor device encapsulated by the encapsulating material; and
a backside redistribution structure over a backside of the encapsulated semiconductor device and comprising a dummy pattern electrically insulated from the semiconductor device and a dielectric layer over the dummy pattern and comprising a marking pattern for revealing a part of the dummy pattern,
wherein the dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package.
 
13. A semiconductor package, comprising:
an encapsulated semiconductor device comprising an encapsulating material and a semiconductor device encapsulated by the encapsulating material; and
a backside redistribution structure over a backside of the encapsulated semiconductor device and comprising:
a dummy pattern comprising a plurality of first dummy pads and a plurality of second dummy pads surrounding the first dummy pads, and a size of each of the first dummy pads is substantially greater than a size of each of the second dummy pads; and
a dielectric layer over the dummy pattern and comprising a marking pattern for revealing a part of the plurality of first dummy pads.
 
18. A semiconductor package, comprising:
an encapsulated semiconductor device comprising an encapsulating material and a semiconductor device laterally encapsulated by the encapsulating material; and
a backside redistribution structure over a backside of the encapsulated semiconductor device and comprising:
a conductive layer comprising a circuit pattern electrically connected to the semiconductor device and a dummy pattern electrically insulated from the semiconductor device and the circuit pattern; and
a dielectric layer over the conductive layer and comprising a marking pattern for revealing a part of the dummy pattern and a bump receiving pattern for revealing a part of the circuit pattern; and
a plurality of conductive bumps disposed in the bump receiving pattern and electrically connected to the circuit pattern.