US 12,261,125 B2
Method for forming chip package structure
Heh-Chang Huang, Hsinchu (TW); Fu-Jen Li, Hsinchu (TW); Pei-Haw Tsao, Tai-chung (TW); and Shyue-Ter Leu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,480.
Application 18/361,480 is a division of application No. 17/244,754, filed on Apr. 29, 2021, granted, now 11,804,445.
Prior Publication US 2023/0378079 A1, Nov. 23, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a first chip structure comprising a first substrate and a first interconnect layer over the first substrate;
a second chip structure over the first interconnect layer, wherein the second chip structure comprises a second substrate and a second interconnect layer, the second interconnect layer is between the second substrate and the first interconnect layer, and the first interconnect layer and the second interconnect layer are between the first substrate and the second substrate;
a first conductive bump connected between the first interconnect layer and the second chip structure;
a conductive pillar over the first interconnect layer;
a molding layer over the first interconnect layer, the first chip structure, the second chip structure, and the conductive pillar; and
a second conductive bump embedded in the molding layer and over a first top surface of the conductive pillar, wherein a first bottom surface of the second conductive bump is higher than a second top surface of the second chip structure,
a portion of the molding layer is between the second conductive bump and a peripheral portion of the first top surface of the conductive pillar, the second conductive bump extends to a central portion of the first top surface of the conductive pillar, and a thickness of the portion of the molding layer decreases toward the central portion of the first top surface of the conductive pillar.