US 12,261,122 B2
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
Atul Madhavan, Portland, OR (US); Nicholas J. Kybert, Portland, OR (US); Mohit K. Haran, Hillsboro, OR (US); and Hiten Kothari, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 19, 2023, as Appl. No. 18/370,198.
Application 17/841,479 is a division of application No. 16/147,541, filed on Sep. 28, 2018, granted, now 11,393,754, issued on Jul. 19, 2022.
Application 18/370,198 is a continuation of application No. 17/841,479, filed on Jun. 15, 2022.
Prior Publication US 2024/0006322 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 29/518 (2013.01); H01L 21/02164 (2013.01); H01L 21/0228 (2013.01); H01L 21/0276 (2013.01); H01L 21/31144 (2013.01); H01L 29/45 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor fin;
a gate structure over the semiconductor fin, the gate structure including a gate insulating layer thereon;
a conductive trench contact structure laterally spaced apart from the gate structure, the conductive trench contact structure including a trench insulating layer thereon;
a first dielectric etch stop layer directly on and continuous over the trench insulating layer and the gate insulating layer;
a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer;
an interlayer dielectric material on the second dielectric etch stop layer;
an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in the trench insulating layer; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive trench contact structure.