US 12,261,120 B2
Three-dimensional (3D) semiconductor memory device and electronic system including the same
Haemin Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 2, 2021, as Appl. No. 17/391,445.
Claims priority of application No. 10-2020-0154241 (KR), filed on Nov. 18, 2020.
Prior Publication US 2022/0157726 A1, May 19, 2022
Int. Cl. H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/535 (2013.01) [H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) semiconductor memory device comprising:
a peripheral circuit structure, an intermediate insulating layer and a cell array structure, which are sequentially stacked,
the cell array structure including
a first semiconductor substrate including a cell array region and a connection region,
a stack structure including electrode layers and electrode interlayer insulating layers alternately stacked on the first semiconductor substrate,
a planarization insulating layer covering an end portion of the stack structure on the connection region,
a first through-via penetrating the planarization insulating layer, the first semiconductor substrate and the intermediate insulating layer, and
the first through-via connecting one of the electrode layers to the peripheral circuit structure,
the first through-via including a first via portion and a second via portion connected to each other,
the first via portion penetrating the planarization insulating layer and having a first width,
the second via portion penetrating the intermediate insulating layer and having a second width greater than the first width, and
a flat area between the first via portion and the second via portion at a boundary between the first via portion and the second via portion.
 
13. An electronic system comprising:
a semiconductor device including a peripheral circuit structure, an intermediate insulating layer, and a cell array structure which are sequentially stacked, and the semiconductor device further including an input/output pad electrically connected to the peripheral circuit structure,
the cell array structure including a first substrate including a cell array region and a connection region, a stack structure comprising electrode layers and electrode interlayer insulating layers which are alternately stacked on the first substrate, a planarization insulating layer covering an end portion of the stack structure on the connection region, a substrate insulating pattern, and a first through-via,
the first through-via penetrating the planarization insulating layer, the substrate insulating pattern, the first substrate and the intermediate insulating layer,
the substrate insulating pattern being between the first substrate and the first through-via and the substrate insulating pattern being between than the planarization insulating layer and the intermediate insulating layer,
the first through-via connecting one of the electrode layers to the peripheral circuit structure,
the planarization insulating layer having a first through-hole having a first width,
the intermediate insulating layer having a second through-hole having a second width greater than the first width,
a flat area between the first through-hole and the second through-hole at a boundary between the first through-hole and the second through-hole, and
the first through-via is in the first through-hole and the second through-hole; and
a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device.