US 12,261,114 B2
Metallization stacks with self-aligned staggered metal lines
Elijah V. Karpov, Portland, OR (US); Christopher J. Jezewski, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); Nafees A. Kabir, Portland, OR (US); and Matthew V. Metz, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 11, 2020, as Appl. No. 17/017,735.
Prior Publication US 2022/0084942 A1, Mar. 17, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/76877 (2013.01); H01L 23/5226 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a support structure;
a first metallization layer, comprising two first electrically conductive lines; and
a second metallization layer, comprising a second electrically conductive line and an interconnect coupled to a sidewall of the second electrically conductive line and one of the two first electrically conductive lines,
wherein:
the first metallization layer is between the support structure and the second metallization layer,
projections of the two first electrically conductive lines and of the second electrically conductive line onto the support structure are substantially parallel,
the projection of the second electrically conductive line is between the projections of the two first electrically conductive lines, and
a lower face of the interconnect and a lower face of the second electrically conductive line are in a single first plane that is substantially parallel to the support structure.