| CPC H01L 23/528 (2013.01) [H10B 53/30 (2023.02)] | 18 Claims |

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1. A memory device, comprising a bit line group comprising a first bit line and a second bit line, the bit line group comprising a first segment, a second segment, a twist segment conductively connected to the first segment of the bit line group and the second segment of the bit line group, and at least one dummy bit line extending in a first lateral direction, the at least one dummy bit line being adjacent to the bit line group in a fourth lateral direction perpendicular to the first lateral direction, wherein:
the first segment of the bit line group comprises a first portion of the first bit line and a first portion of the second bit line, the second segment of the bit line group comprises a second portion of the first bit line and a second portion of the second bit line, and the twist segment of the bit line group comprises a third portion of the first bit line and a third portion of the second bit line;
the first and second portions of the first bit line and the second bit line each extends in the first lateral direction; and
the third portion of the first bit line is conductively connected to the first and second portions of the first bit line, and the third portion of the second bit line is conductively connected to the first and second portions of the second bit line, the third portion of the first bit line extending in a second lateral direction different from the first lateral direction, the third portion of the second bit line extending in a third lateral direction different from the first lateral direction and the second lateral direction.
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