US 12,261,111 B2
Memory devices and related methods of forming a memory device
Kunal R. Parekh, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 8, 2024, as Appl. No. 18/600,146.
Application 18/175,398 is a division of application No. 16/905,698, filed on Jun. 18, 2020, granted, now 11,699,652, issued on Jul. 11, 2023.
Application 18/600,146 is a continuation of application No. 18/175,398, filed on Feb. 27, 2023, granted, now 11,929,323.
Prior Publication US 2024/0213150 A1, Jun. 27, 2024
Int. Cl. H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01)
CPC H01L 23/5226 (2013.01) [G11C 7/18 (2013.01); H01L 23/5283 (2013.01); H01L 24/05 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H01L 2924/1431 (2013.01); H01L 2924/1443 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a control circuitry structure including control logic circuitry; and
a memory array structure vertically overlying and bonded to the control circuitry structure, the memory array structure comprising:
digit line structures;
a stack structure vertically overlying the digit line structures and comprising tiers respectively including conductive material and insulative material vertically neighboring the conductive material;
a source structure comprising doped semiconductor material vertically overlying the stack structure; and
pillar structures vertically extending through the stack structure and coupled to the digit line structures and the source structure, the pillar structures respectively comprising:
an upper boundary substantially coplanar with an upper surface of the doped semiconductor material of the source structure; and
a lower boundary substantially coplanar with a lower surface of the stack structure.