US 12,261,106 B2
Semiconductor package
Hyeonjeong Hwang, Cheonan-si (KR); Kyoung Lim Suk, Suwon-si (KR); Seokhyun Lee, Hwaseong-si (KR); and Jaegwon Jang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 24, 2021, as Appl. No. 17/535,093.
Claims priority of application No. 10-2021-0046062 (KR), filed on Apr. 8, 2021.
Prior Publication US 2022/0328389 A1, Oct. 13, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/20 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/211 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/3511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first redistribution substrate including first interconnection layers that are sequentially stacked on each other, wherein the first interconnection layers consist of all of the interconnection layers for the first redistribution substrate;
a semiconductor chip mounted on the first redistribution substrate;
a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip;
a second redistribution substrate disposed on the mold layer, the second redistribution substrate including second interconnection layers that are sequentially stacked on each other, wherein the second interconnection layers consist of all of the interconnection layers for the second redistribution substrate;
a connection terminal disposed beside the semiconductor chip to connect the first redistribution substrate and the second redistribution substrate to each other; and
outer terminals disposed on a bottom surface of the first redistribution substrate,
wherein:
each of the first interconnection layers comprises a first insulating layer and a first wire pattern that is provided in the first insulating layer,
each of the second interconnection layers comprises a second insulating layer and a second wire pattern that is provided in the second insulating layer,
a thickness of the first redistribution substrate is substantially equal to a thickness of the second redistribution substrate, and
a first thickness of each of the first interconnection layers is smaller than a second thickness of each of the second interconnection layers.