US 12,261,105 B2
Semiconductor package
Myungsam Kang, Hwaseong-si (KR); Youngchan Ko, Seoul (KR); Jeongseok Kim, Cheonan-si (KR); Kyung Don Mun, Hwaseong-si (KR); and Bongju Cho, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 18, 2023, as Appl. No. 18/098,158.
Application 18/098,158 is a continuation of application No. 17/228,784, filed on Apr. 13, 2021, granted, now 11,569,158.
Claims priority of application No. 10-2020-0104111 (KR), filed on Aug. 19, 2020.
Prior Publication US 2023/0154836 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/3171 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2224/16235 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution substrate that includes a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern having a line part that extends horizontally and a via part that extends vertically;
a passivation layer on a top surface of the redistribution substrate;
a conductive pillar that penetrates through the passivation layer, the conductive pillar in contact with the wiring pattern at the via part;
a semiconductor chip including a chip pad on the conductive pillar; and
a connection terminal between the top surface of the conductive pillar and a bottom surface of the chip pad;
wherein a bottom surface of the conductive pillar is coplanar with a bottom surface of the passivation layer, and
wherein the passivation layer contacts a portion of a lateral surface of the conductive pillar.