US 12,261,104 B2
Semiconductor package and method of fabricating the same
Hyeonjeong Hwang, Cheonan-si (KR); Dongkyu Kim, Anyang-si (KR); Minjung Kim, Cheonan-si (KR); and Yeonho Jang, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 14, 2022, as Appl. No. 17/670,635.
Claims priority of application No. 10-2021-0085055 (KR), filed on Jun. 29, 2021.
Prior Publication US 2022/0415771 A1, Dec. 29, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49816 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction;
a semiconductor chip mounted on a top surface of the redistribution substrate; and
an outer terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an under-bump pattern;
a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern;
a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer; and
a redistribution pattern on the under-bump pattern,
wherein the outer terminal is disposed on a bottom surface of the under-bump pattern,
wherein a level of a top surface of the protection pattern on the top surface of the under-bump pattern is higher than a level of a bottom surface of the redistribution insulating layer, and
wherein the top surface of the protection pattern contacts the redistribution insulating layer and the redistribution pattern.