US 12,261,103 B2
Semiconductor package
Yonghwan Kwon, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 5, 2022, as Appl. No. 17/647,144.
Claims priority of application No. 10-2021-0069883 (KR), filed on May 31, 2021.
Prior Publication US 2022/0384322 A1, Dec. 1, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 25/105 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first redistribution substrate;
a semiconductor chip disposed on a top surface of the first redistribution substrate;
a molding layer disposed on the first redistribution substrate, wherein the molding layer covers the semiconductor chip;
a second redistribution substrate disposed on the molding layer, wherein the second redistribution substrate includes a dielectric layer, a redistribution pattern, and a conductive pad, wherein the dielectric layer includes
a lower opening that exposes the conductive pad, and
an upper opening connected to the lower opening, wherein a width of the upper opening is greater than a width of the lower opening; and
a redistribution pad disposed on the conductive pad, wherein the redistribution pad covers a sidewall of the lower opening and at least a portion of a bottom surface of the upper opening,
wherein a top surface of the dielectric layer is located at a higher level than a first top surface of the redistribution pad,
wherein the first top surface of the redistribution pad is located on the bottom surface of the upper opening.