US 12,261,093 B2
Semiconductor packages having a dam structure
Dongho Kim, Asan-si (KR); Jongbo Shim, Asan-si (KR); Hwanpil Park, Hwaseong-si (KR); and Jangwoo Lee, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 9, 2022, as Appl. No. 17/883,726.
Application 17/883,726 is a continuation of application No. 16/928,159, filed on Jul. 14, 2020, granted, now 11,437,293.
Claims priority of application No. 10-2020-0012460 (KR), filed on Feb. 3, 2020.
Prior Publication US 2022/0384291 A1, Dec. 1, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3135 (2013.01) [H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate having first and third sides opposing each other and second and fourth sides connecting the first and third sides, the substrate including bonding pads adjacent to the first side, the second side, and the fourth side, and upper pads farther from the first side, the second side, and the fourth side than the bonding pads;
a lower semiconductor chip disposed on the substrate, and electrically connected to the upper pads by bumps, the lower semiconductor chip having a first side surface opposing the first side of the substrate, a second side surface opposing the second side of the substrate, a third side surface opposing the third side of the substrate, and a fourth side surface opposing the fourth side of the substrate;
at least one upper semiconductor chip disposed on the lower semiconductor chip, and electrically connected to the bonding pads by bonding wires;
a dam structure including a first dam and a second dam, connected to each other and surrounding the lower semiconductor chip in a single closed loop shape on the substrate; and
an underfill disposed inside the dam structure,
wherein the second side and the fourth side each have a first portion adjacent to the bonding pads and a second portion, other than the first portion,
wherein a first linear segment of the first dam is spaced apart from the first side surface of the lower semiconductor chip by a first distance between the first side of the substrate and the first side surface of the lower semiconductor chip, a second linear segment of the first dam is spaced apart from the second side surface of the lower semiconductor chip by the first distance between the first portion of the second side of the substrate and the second side surface of the lower semiconductor chip, and a fourth linear segment of the first dam is spaced apart from the fourth side surface of the lower semiconductor chip by the first distance between the first portion of the fourth side of the substrate and the fourth side surface of the lower semiconductor chip,
wherein a first linear segment of the second dam is spaced apart from the second side surface of the lower semiconductor chip by a second distance, greater than the first distance, between the second portion of the second side of the substrate and the second side surface of the lower semiconductor chip, and a second linear segment of the second dam is spaced apart from the fourth side surface of the lower semiconductor chip by the second distance between the second portion of the fourth side of the substrate and the fourth side surface of the lower semiconductor chip,
wherein a length of the first linear segment of the first dam is greater than a length of the first side surface of the lower semiconductor chip,
wherein the lower semiconductor chip is one semiconductor chip, and
wherein the lower semiconductor chip extends across a majority of an area inside the first dam and a majority of an area inside the second dam.