US 12,261,091 B2
Chip integration into cavities of a host wafer using lateral dielectric material bonding
Florian Herrault, Agoura Hills, CA (US); Isaac Rivera, Buena Park, CA (US); Daniel S. Green, McLean, VA (US); and James F. Buckwalter, Santa Barbara, CA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Jun. 12, 2023, as Appl. No. 18/333,460.
Application 18/333,460 is a division of application No. 18/155,607, filed on Jan. 17, 2023, granted, now 11,756,848.
Prior Publication US 2024/0243026 A1, Jul. 18, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/3114 (2013.01) [H01L 21/561 (2013.01); H01L 24/96 (2013.01); H01L 2224/96 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An electronic assembly comprising:
a backside capping layer having a top surface and a back surface;
a wafer having a front surface and a back surface, the back surface of the wafer bonded to the top surface of the backside capping layer except for cavities in the wafer formed over a plurality of areas of the top surface of the backside capping layer, the cavities having side surfaces;
a plurality of chiplets having a backside and a frontside, the backside of the chiplets bonded directly to at least a portion of the plurality of areas of the top surface of the backside capping layer;
a lateral dielectric material between side surfaces of the chiplets and the side surfaces of the cavities,
wherein the lateral dielectric material bonds the side surfaces of the chiplets to the side surfaces of the cavities; and
direct interconnects of conductive material from the plurality of chiplets, directly on the lateral dielectric material, and to wafer electrical routing of the wafer, wherein the wafer includes at least one layer of a semiconductor wafer material; and wherein the semiconductor wafer material includes passive integrated components and active microelectronic devices.