US 12,261,084 B2
Fan-out wafer level packaging of semiconductor devices
George Chang, Tempe, AZ (US); Yusheng Lin, Phoenix, AZ (US); Gordon M. Grivna, Mesa, AZ (US); and Takashi Noma, Ota (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Jun. 15, 2021, as Appl. No. 17/304,136.
Application 17/304,136 is a division of application No. 16/145,783, filed on Sep. 28, 2018, granted, now 11,043,420.
Prior Publication US 2021/0305096 A1, Sep. 30, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 21/6836 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 24/94 (2013.01); H01L 24/95 (2013.01); H01L 24/96 (2013.01); H01L 21/304 (2013.01); H01L 21/563 (2013.01); H01L 2224/94 (2013.01); H01L 2224/951 (2013.01); H01L 2224/96 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A fan-out wafer level package (FOWLP) semiconductor device, comprising:
a semiconductor die having:
an active surface;
a backside surface opposite the active surface;
a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface; and
a plurality of conductive bumps disposed on the active surface;
an insulating layer disposed on a first portion of the active surface and excluded from a second portion of the active surface, the first portion of the active surface being disposed between the plurality of conductive bumps, the second portion of the active surface being disposed between the plurality of conductive bumps and a perimeter edge of the active surface, the insulating layer respectively contacting, at most, two sides of conductive bumps of the plurality of conductive bumps;
a molding compound, the molding compound:
encapsulating the backside surface, and the plurality of side surfaces; and
partially encapsulating the active surface, such that the second portion of the active surface is encapsulated in the molding compound and the molding compound is excluded from the first portion of the active surface; and
a signal distribution structure disposed on the plurality of conductive bumps, disposed on the insulating layer, and disposed on the molding compound, the signal distribution structure being configured to provide respective electrical connections to the plurality of conductive bumps.