US 12,261,079 B2
Method for fabricating a strained semiconductor-on-insulator substrate
Walter Schwarzenbach, Saint Nazaire Les Eymes (FR); Guillaume Chabanne, Le Touvet (FR); and Nicolas Daval, Goncelin (FR)
Assigned to SOITEC, Bernin (FR)
Filed by Soitec, Bernin (FR)
Filed on Aug. 14, 2023, as Appl. No. 18/449,298.
Application 18/449,298 is a continuation of application No. 17/207,202, filed on Mar. 19, 2021, granted, now 11,728,207.
Application 17/207,202 is a continuation of application No. 16/301,276, granted, now 10,957,577, previously published as PCT/EP2017/061793, filed on May 17, 2017.
Claims priority of application No. 1654369 (FR), filed on May 17, 2016.
Prior Publication US 2023/0386896 A1, Nov. 30, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/762 (2006.01)
CPC H01L 21/76275 (2013.01) [H01L 21/76254 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A strained semiconductor-on-insulator substrate, the substrate comprising:
a base substrate;
a partially relaxed monocrystalline semiconductor material disposed on the base substrate;
a dielectric layer disposed on the partially relaxed monocrystalline semiconductor material;
a partially strained monocrystalline semiconductor layer disposed on the dielectric layer;
a bonding interface buried within the dielectric layer or located between the dielectric layer and the partially strained monocrystalline semiconductor layer; and
trenches extending from a surface of the partially strained monocrystalline semiconductor layer through the partially strained monocrystalline semiconductor layer, through the dielectric layer, through the partially relaxed monocrystalline semiconductor material, and only partially into the base substrate.