US 12,261,057 B2
Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
Kevin Lin, Beaverton, OR (US); Robert Lindsey Bristol, Portland, OR (US); and Alan M. Myers, Beaverton, OR (US)
Assigned to Tahoe Research, Ltd., Dublin (IE)
Filed by Tahoe Research, Ltd., Dublin (IE)
Filed on Feb. 3, 2022, as Appl. No. 17/592,442.
Application 17/592,442 is a division of application No. 16/435,240, filed on Jun. 7, 2019, granted, now 11,276,581.
Application 16/435,240 is a division of application No. 15/575,283, granted, now 10,366,903, previously published as PCT/US2015/038145, filed on Jun. 26, 2015.
Prior Publication US 2022/0157619 A1, May 19, 2022
Int. Cl. H01L 21/76 (2006.01); H01L 21/033 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/32139 (2013.01) [H01L 21/0337 (2013.01); H01L 21/76801 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76834 (2013.01); H01L 21/76885 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 2224/16225 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of forming self-aligned features in a semiconductor device, comprising:
forming a hardmask layer, comprising four hardmask materials arranged in a checkered pattern, over a conductive line;
depositing a photoresist material on the hardmask layer;
forming a first opening in the hardmask layer that exposes a top surface of the conductive line by removing a portion of the photoresist material and a portion of a first hardmask material of the four hardmask materials, wherein the exposed top surface of the conductive line comprises a top surface of a first via portion formed over an interconnect line;
removing the first via portion by etching; and
depositing a dielectric fill material into the first opening to replace the removed first via portion of the conductive line.