US 12,261,056 B2
Top via patterning using metal as hard mask and via conductor
Nicholas Anthony Lanzillo, Wynantskill, NY (US); Huai Huang, Clifton Park, NY (US); Hosadurga Shobha, Niskayuna, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); and Chanro Park, Clifton Park, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 30, 2021, as Appl. No. 17/460,624.
Prior Publication US 2023/0067493 A1, Mar. 2, 2023
Int. Cl. H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/32139 (2013.01) [H01L 21/76885 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor structure, the semiconductor structure comprising:
a substrate;
a first metal layer on top of the substrate, wherein the first metal layer includes a lower portion and a via connected to the lower portion, wherein the via is comprised of a same material as the lower portion;
a second metal layer on top of the first metal layer and in direct contact with the via of the first metal layer, wherein a width of the second metal layer is the same as a width of the via of the first metal layer, wherein the second metal layer is comprised of a different material than the first metal layer; and
a dielectric layer in direct contact with sidewalls of the second metal layer and a portion of sidewalls of the first metal layer and on top of at least part of the first metal layer, wherein outer sidewalls of the dielectric layer are flush with sidewalls of the lower portion of the first metal layer.