US 12,261,052 B2
High electron mobility transistor and fabricating method of the same
Ming-Hua Chang, Tainan (TW); Kun-Yuan Liao, Hsinchu (TW); Lung-En Kuo, Tainan (TW); and Chih-Tung Yeh, Taoyuan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Mar. 19, 2024, as Appl. No. 18/608,940.
Application 18/608,940 is a division of application No. 17/515,541, filed on Oct. 31, 2021, granted, now 12,002,681.
Claims priority of application No. 202111185692.8 (CN), filed on Oct. 12, 2021.
Prior Publication US 2024/0222133 A1, Jul. 4, 2024
Int. Cl. H10D 30/01 (2025.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H01L 21/3086 (2013.01) [H01L 21/30621 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 4 Claims
OG exemplary drawing
 
1. A high electron mobility transistor, comprising:
a substrate;
a channel layer, an active layer, a P-type group III-V gate and a metal compound layer disposed on the substrate, wherein the channel layer, the active layer, the P-type group III-V gate and the metal compound layer are disposed from bottom to top, the metal compound layer contacts the P-type group III-V gate, the metal compound layer has two sidewalls which are opposed to each other, two acute angles are respectively formed between one of the two sidewalls and a top surface of the P-type group III-V gate and between the other of the two sidewalls and the top surface of the P-type group III-V gate; and
a source electrode, a drain electrode and a gate electrode disposed on the active layer, wherein the gate electrode is separate from the metal compound layer.