US 12,261,043 B2
Seed layer for ferroelectric memory device and manufacturing method thereof
Chun-Chieh Lu, Taipei (TW); Sai-Hooi Yeong, Hsinchu County (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Nov. 15, 2023, as Appl. No. 18/509,338.
Application 18/509,338 is a continuation of application No. 17/709,284, filed on Mar. 30, 2022, granted, now 11,869,766.
Application 17/709,284 is a continuation of application No. 16/925,267, filed on Jul. 9, 2020, granted, now 11,302,529, issued on Apr. 12, 2022.
Prior Publication US 2024/0087887 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); H10B 51/30 (2023.01)
CPC H01L 21/02516 (2013.01) [H01L 21/02472 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a bottom electrode over a substrate;
depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase;
performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase;
depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; and
performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.