CPC H01L 21/0217 (2013.01) [H01L 21/02208 (2013.01); H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A method comprising:
placing a wafer into a process chamber;
depositing a first silicon nitride layer over the wafer, the depositing comprising:
depositing a first sub layer of the first silicon nitride layer;
performing a first treatment process on the first sub layer using hydrogen as a process gas; and
after the first treatment process, depositing a second sub layer of the first silicon nitride layer over the first sub layer;
patterning the first silicon nitride layer to form a patterned hard mask;
etching the wafer using the patterned hard mask as an etching mask;
removing the patterned hard mask;
depositing a second silicon nitride layer on a gate stack in the wafer and extending on source/drains adjacent the gate stack, wherein the depositing the second silicon nitride layer is free from treatment processes performed using hydrogen as process gases;
annealing the wafer when the second silicon nitride layer is on the gate stack; and
after the annealing, removing the second silicon nitride layer.
|