US 12,261,036 B2
Forming low-stress silicon nitride layer through hydrogen treatment
Wei-Che Hsieh, New Taipei (TW); Ching Yu Huang, Hsinchu (TW); Hsin-Hao Yeh, Taipei (TW); Chunyao Wang, Zhubei (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,508.
Application 18/358,508 is a continuation of application No. 17/809,917, filed on Jun. 30, 2022, granted, now 11,830,727.
Application 17/809,917 is a continuation of application No. 15/983,565, filed on May 18, 2018, granted, now 11,393,674, issued on Jul. 19, 2022.
Prior Publication US 2023/0386826 A1, Nov. 30, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/0217 (2013.01) [H01L 21/02208 (2013.01); H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
placing a wafer into a process chamber;
depositing a first silicon nitride layer over the wafer, the depositing comprising:
depositing a first sub layer of the first silicon nitride layer;
performing a first treatment process on the first sub layer using hydrogen as a process gas; and
after the first treatment process, depositing a second sub layer of the first silicon nitride layer over the first sub layer;
patterning the first silicon nitride layer to form a patterned hard mask;
etching the wafer using the patterned hard mask as an etching mask;
removing the patterned hard mask;
depositing a second silicon nitride layer on a gate stack in the wafer and extending on source/drains adjacent the gate stack, wherein the depositing the second silicon nitride layer is free from treatment processes performed using hydrogen as process gases;
annealing the wafer when the second silicon nitride layer is on the gate stack; and
after the annealing, removing the second silicon nitride layer.