US 12,260,995 B2
Ceramic electronic device and manufacturing method of the same
Kotaro Mizuno, Takasaki (JP)
Assigned to TAIYO YUDEN CO., LTD., Tokyo (JP)
Filed by TAIYO YUDEN CO., LTD., Tokyo (JP)
Filed on Apr. 29, 2024, as Appl. No. 18/649,416.
Application 18/649,416 is a continuation of application No. 17/939,851, filed on Sep. 7, 2022, granted, now 12,002,630.
Claims priority of application No. 2021-161166 (JP), filed on Sep. 30, 2021.
Prior Publication US 2024/0290545 A1, Aug. 29, 2024
Int. Cl. H01G 4/30 (2006.01); C04B 35/468 (2006.01); C04B 35/64 (2006.01); H01G 4/008 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01)
CPC H01G 4/30 (2013.01) [C04B 35/4682 (2013.01); C04B 35/64 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/1227 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A ceramic electronic device comprising:
a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers including Ni as a main phase are alternately stacked,
wherein at least one of the plurality of dielectric layers includes Si, and
wherein one of the plurality of internal electrode layers next to the at least one of the plurality of dielectric layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In,
wherein a peak of a concentration of the additive element and/or a peak of a concentration of Si in the one of the plurality of internal electrode layers and the at least one of the plurality of dielectric layers exist(s) in a region within 15 nm in a thickness direction from an interface between the one of the plurality of internal electrode layers and the at least one of the plurality of dielectric layers.