US 12,260,930 B2
Memory core characteristic screening method and system thereof
Jeong Ho Bang, Milpitas, CA (US); Hyeon Jae Lee, Milpitas, CA (US); Wol Jin Lee, Milpitas, CA (US); Ki Hyung Ryoo, Milpitas, CA (US); Kwang Rae Cho, Milpitas, CA (US); and Sun Byeong Yoon, Milpitas, CA (US)
Assigned to INTEGRATED SILICON SOLUTION INC., Milpitas, CA (US)
Filed by Integrated Silicon Solution Inc., Milpitas, CA (US)
Filed on Dec. 23, 2022, as Appl. No. 18/145,927.
Prior Publication US 2024/0212728 A1, Jun. 27, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 7/1087 (2013.01); G11C 7/12 (2013.01); G11C 8/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory core characteristic screening method, comprising:
performing a command signal transmitting step to configure a processing module to transmit a command signal to a memory device, wherein the command signal comprises a first command and a second command;
performing a first internal operating step, wherein the first internal operating step comprises configuring the memory device to operate a first operation to a first one of a word line, a bit line pair and a column line after a first strobe signal delay time according to the first command;
performing a second internal operating step, wherein the second internal operating step comprises configuring the memory device to operate a second operation to a second one of the word line, the bit line pair and the column line after a second strobe signal delay time according to the second command; and
performing a memory core characteristic screening step, wherein the memory core characteristic screening step comprises configuring the processing module to screen a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time;
wherein the first command and the second command are different from each other and applied on different elements in the memory device;
wherein the processing module comprises one of a memory controller and a tester.