US 12,260,929 B2
Semiconductor device including internal transmission path and stacked semiconductor device using the same
Jinhyung Lee, Gyeonggi-do (KR); Myeong Jae Park, Gyeonggi-do (KR); Su Hyun Oh, Gyeonggi-do (KR); and Chang Kwon Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 27, 2024, as Appl. No. 18/587,961.
Application 18/587,961 is a continuation of application No. 17/554,226, filed on Dec. 17, 2021, granted, now 11,942,181.
Claims priority of application No. 10-2021-0094719 (KR), filed on Jul. 20, 2021.
Prior Publication US 2024/0194232 A1, Jun. 13, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 5/06 (2006.01)
CPC G11C 7/1072 (2013.01) [G11C 5/06 (2013.01); G11C 7/1048 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit configured to generate a transfer signal by decreasing an amplitude of an input signal provided through a first interface and configured to transfer the transfer signal through a transfer path; and
a second circuit configured to generate an output signal by increasing an amplitude of the transfer signal transferred through the transfer path and configured to output the output signal through a second interface,
wherein the second circuit includes a decision feedback equalizer (DFE) configured to regulate a reference level for determining a logic level of the transfer signal.