US 12,260,928 B2
Memory devices with backside boost capacitor and methods for forming the same
Nail Etkin Can Akkaya, Hsinchu (TW); Mahmut Sinangil, Campbell, CA (US); Yih Wang, Hsinchu (TW); and Jonathan Tsung-Yung Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 8, 2022, as Appl. No. 17/835,652.
Claims priority of provisional application 63/314,351, filed on Feb. 25, 2022.
Prior Publication US 2023/0274769 A1, Aug. 31, 2023
Int. Cl. G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01)
CPC G11C 5/145 (2013.01) [G11C 7/12 (2013.01); G11C 11/419 (2013.01); H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell;
a bit line coupled to the memory cell; and
a voltage generator coupled to the bit line and configured to provide a negative voltage to the bit line;
wherein the voltage generator comprises:
a transistor; and
a first capacitor having a first terminal and a second terminal electrically coupled to a drain and a gate of the transistor, respectively; and
wherein the drain and the gate of the transistor are formed on a first side of a substrate, and the first and second terminals of the first capacitor are formed on a second side of the substrate opposite to the first side, wherein the voltage generator comprises a second capacitor having a first terminal and a second terminal electrically coupled to the drain and the gate of the transistor, respectively, wherein the first and second terminals of the second capacitor are formed on the first side of the substrate, and where a capacitance of the first capacitor on the second side of the substrate is greater than a capacitance of the second capacitor on the first side of the substrate.