US 12,260,927 B2
Die-based high and low priority error queues
Gyan Prakash, San Jose, CA (US); and Vijay Sankar, San Jose, CA (US)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 11, 2022, as Appl. No. 17/862,006.
Application 17/862,006 is a continuation of application No. 17/022,848, filed on Sep. 16, 2020, granted, now 11,417,410.
Prior Publication US 2023/0030672 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/40 (2006.01); G06F 9/48 (2006.01); G11C 29/12 (2006.01); G11C 29/26 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G06F 9/4881 (2013.01); G11C 29/1201 (2013.01); G11C 29/26 (2013.01); G11C 29/44 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of scheduling error recovery instructions by a processor communicatively coupled to a NAND memory device comprising an n×m array of NAND memory dies having n channels, each channel of the n channels being communicatively coupled to m NAND memory dies to form n×m die queues each comprising p die priority queues, each NAND memory die of the n×m array is assigned to one of at least two groups, and the die priority queues are grouped to correspond to the at least two groups to which the n×m array of NAND memory dies are assigned, the method comprising:
receiving an indication of a read error responsive to an attempted execution of a read command on a destination die of the n×m array of NAND memory dies;
creating an error recovery instruction in response to the indication of the read error;
determining the destination die of the n×m array of NAND memory dies to which the read command is directed and a priority of the error recovery instruction; and
sending the error recovery instruction to a die priority queue corresponding to the determined destination die and the priority of the error recovery instruction.