US 12,260,926 B2
Loopback datapath for clock quality detection
Matthew Alan Prather, Boise, ID (US); and Won Ho Choi, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 4, 2023, as Appl. No. 18/312,280.
Claims priority of provisional application 63/347,886, filed on Jun. 1, 2022.
Prior Publication US 2023/0395175 A1, Dec. 7, 2023
Int. Cl. G11C 29/12 (2006.01)
CPC G11C 29/12015 (2013.01) [G11C 29/1201 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory device, comprising:
internal clock generation circuitry configured to receive a first set of system clock signals from a host device and configured to generate a first internal clock signal based at least in part on the first set of system clock signals, the first internal clock signal associated with a first set of termination values;
phase generation circuitry configured to generate a first loopback signal based at least in part on the first internal clock signal;
a first loopback path configured to transmit the first loopback signal to enable the host device to determine a new set of termination values; and
one or more mode registers configured to select the new set of termination values, wherein the internal clock generation circuitry is configured to generate a second internal clock signal associated with the new set of termination values.