US 12,260,925 B2
Data integrity check in non-volatile storage
Sugandha Sharma, Pleasanton, CA (US); and Mahim Raj Gupta, Milpitas, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/358,605.
Claims priority of provisional application 63/490,061, filed on Mar. 14, 2023.
Prior Publication US 2024/0312546 A1, Sep. 19, 2024
Int. Cl. G11C 29/12 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more control circuits configured to connect to a memory structure, the memory structure comprising physical blocks having NAND strings, each physical block having a group of word lines, wherein each word line of a physical block connects to all NAND strings in the physical block, wherein each physical block comprises one or more erase blocks, the one or more control circuits configured to:
perform a first data integrity check of data stored in memory cells connected to a first subset of word lines in closed blocks of the erase blocks, the first subset of the word lines being located at a corresponding first set of locations in the closed blocks; and
perform a second data integrity check of data stored in memory cells connected to a second subset of word lines in open blocks of the erase blocks responsive to a determination that more than an allowed number of the first subset of the word lines fail the first data integrity check in a closed block, the second subset of the word lines being located at a corresponding second set of locations in the open blocks, wherein the second data integrity check is not performed for the second subset of word lines in the open blocks prior to more than the allowed number of the first subset of the word lines failing the first data integrity check in the closed block.