| CPC G11C 29/1201 (2013.01) [G11C 11/419 (2013.01); G11C 2029/1204 (2013.01)] | 13 Claims |
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1. A design for testability circuit of a static random access memory (SRAM), wherein
the SRAM comprises a memory cell area and an external control circuit area;
a memory cell array formed by arranging a plurality of memory cells is formed in the memory cell area and memory cells in a same column are connected to a same bit line;
the external control circuit area comprises a write path circuit and a read path circuit;
an output end of the write path circuit and an input end of the read path circuit are both connected to a bit line signal end, the bit line signal end is connected to a corresponding bit line through a write data bit multiplexer, and the bit line signal end is connected to the corresponding bit line through a read data bit multiplexer;
the design for testability circuit comprises a fault diagnosis logic control module;
the fault diagnosis logic control module is configured to control a fault diagnosis mode in a fault diagnosis process, and the fault diagnosis mode comprises a write path circuit detection mode; in the write path circuit detection mode, the write path circuit is in an on state, the write data bit multiplexer is in a selected state, and the read data bit multiplexer is in a deselected state, the read path circuit is in an on state and the memory cell is in a selected state; the write path circuit implements writing of the memory cell, and the read path circuit implements reading of the bit line signal end to implement detection of the write path circuit;
the fault diagnosis mode further comprises a read path circuit detection mode;
in the read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, the memory cell is in a deselected state, the bit line signal end is connected to a test signal outputted by a signal generation circuit, and the read path circuit implements reading of the test signal to implement detection of the read path circuit, wherein the read path circuit comprises a sense amplifier, a read buffer, and a read latch;
an input end of the sense amplifier is connected to the bit line signal end, an output end of the sense amplifier is connected to an input end of the read buffer, an output end of the read buffer is connected to an input end of the read latch, and an output end of the read latch outputs a read signal;
an enable signal connected to an enable end of the sense amplifier is an SAE signal or an SAEN signal; the SAEN signal is an anti-phase signal of the SAE signal;
an enable signal connected to an enable end of the read buffer is an SAE signal or an SAEN signal;
an enable signal connected to an enable end of the read latch is an SAE signal or an SAEN signal;
the fault diagnosis logic control module comprises a DFT signal generation module configured to generate a DFT signal;
in fault diagnosis detection, the DFT signal is provided to the SAE signal;
the write path circuit comprises a write selector, a write driver circuit and a write latch;
an output end of the write driver circuit is connected to an input end of the write selector, an output end of the write selector acts as the output end of the write path circuit, an input end of the write driver circuit is connected to an output end of the write latch, and an input end of the write latch is connected to a write signal;
an enable signal connected to an enable end of the write selector is a WE signal or WEN signal, and the WEN signal is an anti-phase signal of the WE signal; and
an enable signal connected to an enable end of the write driver circuit is a WE signal or WEN signal.
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