| CPC G11C 29/12005 (2013.01) [G11C 8/12 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/3445 (2013.01); G11C 29/12 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2211/4068 (2013.01)] | 20 Claims |
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1. A nonvolatile memory device, comprising:
a memory cell array comprising a plurality of mats corresponding to different bit-lines among a plurality of bit-lines,
wherein each of the plurality of mats comprises at least one memory block comprising a plurality of cell strings, each of the plurality of cell strings comprises a string selection transistor, a plurality of memory cells and a ground selection transistor, which are connected in series and disposed in a vertical direction between a bit-line among the plurality of bit-lines and a common source line;
an address decoder coupled to the memory cell array through a plurality of word-lines,
wherein the address decoder is configured to provide word-line voltages to the memory cell array;
at least one leakage detector commonly coupled to the plurality of mats at a sensing node in the address decoder; and
a control circuit configured to control the address decoder and the at least one leakage detector,
wherein the control circuit is configured to:
perform a first leakage detection operation on M mats selected from the plurality of mats to determine a leakage of at least a portion of word-lines of the M mats in an N multi-mat mode during which N mats from among the plurality of mats operate concurrently,
wherein M is a natural number greater than one, and Nis a natural number greater than one, and
in response to the leakage of at least the portion of word-lines of the M mats being detected based on a result of the first leakage detection operation:
inhibit at least one mat of the M mats after performing the first leakage detection operation, and
perform a second leakage detection operation on at least one target mat from among the M mats except the inhibited at least one mat after performing the first leakage detection operation,
wherein the control circuit is configured to perform the first leakage detection operation by, during a word-line set-up period and while applying a first voltage to a block word-line that is coupled to each gate of a plurality of pass transistors which respectively connect a string selection line, a plurality of word-lines and a ground selection line of each of the M mats to a plurality of driving lines, applying a second voltage to the plurality of driving lines, commonly coupled to the sensing node, to provide the plurality of word-lines with a third voltage,
wherein the control circuit is configured to perform the second leakage detection operation by deactivating a second block word-line of the inhibited at least one mat during the word-line set-up period, during a word-line development period and during a sensing period.
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