US 12,260,921 B2
Sense amplifier architecture providing reduced program verification time
Hiroki Yabe, Yokohama (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 10, 2022, as Appl. No. 17/838,072.
Prior Publication US 2023/0402111 A1, Dec. 14, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/065 (2013.01); G11C 7/1048 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for sensing a data state of a memory cell, the method comprising:
connecting a first sensing node and a second sensing node to an internal bitline of a sensing amplifier to simultaneously discharge a first capacitor connected to the first sensing node and a second capacitor connected to the second sensing node through the memory cell;
after a first sensing period, disconnecting the second sensing node from the internal bitline, wherein the second sensing node includes a first voltage level based on discharging the second capacitor;
after a second sensing period, disconnecting the first sensing node from the internal bitline, wherein the first sensing node includes a second voltage level based on discharging the first capacitor; and
latching a first sensing result and a second sensing result based on the first and second voltage levels, respectively, wherein a data state of the memory cell is based on the first and second voltage levels, and wherein the second sensing period comprises the first sensing period and is longer than the first sensing period.