US 12,260,919 B2
Systems and methods involving hardware-based reset of unresponsive memory devices
Vipul Patel, Santa Clara, CA (US); and Theodore Pekny, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 21, 2022, as Appl. No. 17/845,785.
Application 17/845,785 is a continuation of application No. 17/188,153, filed on Mar. 1, 2021, granted, now 11,386,964.
Application 17/188,153 is a continuation of application No. 16/543,271, filed on Aug. 16, 2019, granted, now 10,937,506, issued on Mar. 2, 2021.
Prior Publication US 2022/0319612 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/22 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/22 (2013.01) [G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a write protect pin; and
a timeout circuit coupled to the write protect pin, the timeout circuit having an output that causes generation of a reset signal for resetting the memory device in response to determining that the timeout circuit has been activated for longer than a predetermined time duration while the memory device is in a busy state.