US 12,260,918 B2
Memory devices and methods of processing security data thereof
Yoo-jung Lee, Hwaseong-si (KR); Jang-seok Choi, Seongnam-si (KR); Duk-sung Kim, Hwaseong-si (KR); and Hyun-joong Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 4, 2022, as Appl. No. 17/712,579.
Application 17/712,579 is a continuation of application No. 16/529,100, filed on Aug. 1, 2019, abandoned.
Claims priority of application No. 10-2018-0154693 (KR), filed on Dec. 4, 2018.
Prior Publication US 2022/0230688 A1, Jul. 21, 2022
Int. Cl. G11C 16/22 (2006.01); G06F 12/14 (2006.01); G06F 21/45 (2013.01); G06F 21/62 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2006.01); G11C 11/16 (2006.01); G11C 11/4078 (2006.01); G11C 11/409 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/22 (2013.01) [G06F 12/1466 (2013.01); G06F 21/45 (2013.01); G06F 21/62 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/4078 (2013.01); G11C 11/409 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array; and
a security management circuit configured to enter a memory allocation phase for a security region in response to a first mode signal and a write command that are received through a same command line from a host system including a host and a memory controller, and to allocate a region in the memory cell array to the security region based on a physical address received through an address line from the memory controller, wherein the security management circuit is electrically connected between the memory controller and the memory cell array, and wherein the host is configured to generate a virtual address that corresponds to the security region, and the memory controller is configured to map the virtual address to the physical address and provide the physical address to the security management circuit via the address line,
wherein the security management circuit is further configured to compare a password received from the memory controller with a guard key of the security region, in response to a memory operation command for the security region received from the host system, and to control a data operation for the security region based on a result of the comparison,
wherein the memory cell array comprises the security region and a normal region different from the security region,
wherein the normal region is connected to at least one word line, and the security region is separated from the at least one word line,
wherein the first mode signal is received through the command line before receiving the write command or simultaneously with the receiving of the write command,
wherein the memory device is main volatile memory of the host system, and
wherein the memory device is separated from the host system, and the security management circuit is distinct from the memory controller.