US 12,260,916 B2
Partial block handling in a non-volatile memory device
Zhongguang Xu, San Jose, CA (US); Nicola Ciocchini, Boise, ID (US); Zhenlei Shen, Milpitas, CA (US); Charles See Yeung Kwong, Redwood City, CA (US); Murong Lang, San Jose, CA (US); Ugo Russo, Boise, ID (US); and Niccolo' Righetti, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 4, 2024, as Appl. No. 18/404,827.
Application 18/404,827 is a continuation of application No. 17/739,741, filed on May 9, 2022.
Prior Publication US 2024/0145010 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
performing one or more program operations on memory cells associated with one or more wordlines of a plurality of wordlines of a segment of the memory device;
determining that a predetermined period of time associated with programming the segment of the memory device has expired; and
responsive to determining that the predetermined period of time has expired, initiating a partial block handling protocol for the segment of the memory device, wherein the partial block handling protocol comprises programming memory cells associated with two or more remaining wordlines of the plurality of wordlines of the segment with padding data having a mixed data pattern.