US 12,260,914 B2
Level shifting in all levels programming of a memory device in a memory sub-system
Sheyang Ning, San Jose, CA (US); and Lawrence Celso Miranda, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 18, 2022, as Appl. No. 17/675,447.
Claims priority of provisional application 63/225,772, filed on Jul. 26, 2021.
Claims priority of provisional application 63/209,592, filed on Jun. 11, 2021.
Claims priority of provisional application 63/166,474, filed on Mar. 26, 2021.
Prior Publication US 2022/0310167 A1, Sep. 29, 2022
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of memory cells configured as a multi-level cell (MLC) memory; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a set of memory cells of the memory array to be programmed during a programming operation;
causing, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
performing a program verify operation corresponding to the first programming level;
comparing a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied; and
executing a level shifting operation in response to the condition being satisfied, wherein the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.