US 12,260,913 B2
Hyperdimensional computing device
Yu-Hsuan Lin, Taichung (TW); and Po-Hao Tseng, Taichung (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Feb. 9, 2023, as Appl. No. 18/166,484.
Prior Publication US 2024/0274199 A1, Aug. 15, 2024
Int. Cl. G11C 5/00 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A hyperdimensional computing device, comprising:
a non-volatile memory cell array, coupled to a plurality of first word lines, the memory cell array having a plurality of first memory cell groups, a plurality of first memory cells of each of the first memory cell groups being coupled to a same first word line of the first word lines, the first memory cell groups respectively storing a plurality of data vectors; and
a first operation circuit, coupled to a plurality of first bit lines of the non-volatile memory cell array, receiving at least one of the data vectors through the bit lines, and generating a bundled data vector according to the at least one of the data vectors,
wherein each of the data vectors is an n-gram vector, and the data vectors comprise all permutations and combinations of a plurality of characters.