| CPC G11C 16/0483 (2013.01) [G11C 16/10 (2013.01); G11C 16/3454 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line;
a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal on the basis of a command signal and an address signal;
a page buffer group including a plurality of page buffers and configured to:
form each of the plurality of bit lines to a preset voltage level on the basis of the page buffer control signal during threshold voltage variation verification on a plurality of select transistors included in the plurality of memory strings, and
generate a threshold voltage variation result on the basis of whether a current path is formed in each of the plurality of bit lines;
a voltage generation circuit that generates a threshold verification voltage and a pass voltage on the basis of the voltage control signal; and
a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage on the basis of the drive address signal and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.
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