| CPC G11C 13/004 (2013.01) [G11C 13/0004 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01)] | 20 Claims |
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1. A sense amplifier architecture comprising:
a plurality of sense amplifier reading branches coupled to a non-volatile memory device having a plurality of memory cells,
the plurality of memory cells including a plurality of groups of memory cells that store respective codewords formed by stored logic states,
each of the plurality of sense amplifier reading branches coupled to a respective memory cell of the plurality of memory cells, and configured to provide an output signal indicative of a cell current flowing through the respective memory cell,
each of the plurality of sense amplifier reading branches including:
a sense transistor coupled to an input node and configured to provide the output signal,
a forcing transistor having a drain terminal coupled to an output node on which the output signal is provided, a source terminal coupled to a reference terminal, and a gate terminal configured to receive an enabling signal, and
a switch element that couples the output node to the input node,
the sense transistor coupled between the source terminal of the forcing transistor and the reference terminal, and having a gate terminal coupled to the output node;
a comparison stage configured to perform a comparison between cell currents of memory cells in a group of memory cells of the plurality of groups of memory cells; and
a logic stage configured to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells.
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