US 12,260,908 B2
Spike current suppression in a memory array
Sundaravadivel Rajarajan, South Jordan, UT (US); Srivatsan Venkatesan, Sandy, UT (US); Iniyan Soundappa Elango, Lehi, UT (US); and Robert Douglas Cassel, Lehi, UT (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 13, 2022, as Appl. No. 17/943,520.
Application 17/943,520 is a continuation of application No. 17/222,864, filed on Apr. 5, 2021.
Prior Publication US 2023/0018390 A1, Jan. 19, 2023
Int. Cl. G11C 13/00 (2006.01); G06F 3/06 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/003 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10B 63/80 (2023.02); H10N 70/041 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/882 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an access line having a first portion and a second portion, wherein a gap physically separates the first portion and the second portion, and each of the first and second portions is configured to access respective memory cells on opposite sides of the gap; and
a via electrically connected to the first and second portions, the via configured for coupling a voltage to the first and second portions.