US 12,260,907 B2
Shared decoder architecture for three-dimensional memory arrays
Christophe Vincent Antoine Laurent, Agrate Brianza (IT); Andrea Martinelli, Bergamo (IT); Efrem Bolandrina, Fiorano al Serio (IT); and Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 29, 2024, as Appl. No. 18/622,033.
Application 18/622,033 is a division of application No. 17/655,957, filed on Mar. 22, 2022, granted, now 11,967,372.
Prior Publication US 2024/0321349 A1, Sep. 26, 2024
Int. Cl. G11C 13/04 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0023 (2013.01) [G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method, comprising:
performing an access operation for a memory cell that is coupled with a word line and a pillar extending through a plurality of levels of a memory array, the access operation comprising:
coupling the pillar with a bit line by biasing a first gate line and a second gate line to a first voltage based at least in part on applying a first signal to a first transistor coupled with the first gate line and a first signal node and on applying a second signal to a second transistor coupled with a supply node and the first gate line; and
biasing the bit line to a second voltage based at least in part on biasing the first gate line and the second gate line to the first voltage, wherein the second voltage is less than the first voltage.