US 12,260,905 B2
SRAM with improved write performance and write operation method thereof
Seong Ook Jung, Seoul (KR); Keon Hee Cho, Seoul (KR); Ji Sang Oh, Seoul (KR); and Min June Yeo, Seoul (KR)
Assigned to UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed by UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed on Feb. 14, 2023, as Appl. No. 18/168,943.
Claims priority of application No. 10-2022-0060393 (KR), filed on May 17, 2022.
Prior Publication US 2023/0377639 A1, Nov. 23, 2023
Int. Cl. G11C 11/418 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An SRAM comprising:
a memory cell array in which a plurality of memory cells each defined by a word line and a bit line pair are arranged;
a write driver that applies a write voltage corresponding to an applied data to the bit line pair connected to a memory cell; and
a word line driver activating the word line after the write voltage is applied to the bit line pair and after a pre-develop period,
wherein the pre-develop period is determined according to a time having a first voltage and a second voltage lower than the first voltage, by the write voltage applied to the bit line pair,
wherein the SRAM further include:
a write auxiliary circuit activated during the pre-develop period to temporarily apply a third voltage having a lower voltage level than the second voltage to a line to which the second voltage is applied among the bit line pair.