US 12,260,904 B2
Memory device with additional write bit lines
Hidehiro Fujiwara, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); Jui-Che Tsai, Tainan (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 15, 2022, as Appl. No. 18/066,306.
Application 18/066,306 is a continuation of application No. 16/870,030, filed on May 8, 2020, granted, now 11,532,351.
Prior Publication US 2023/0118295 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01); G11C 7/12 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising a plurality of columns, wherein each column of the plurality of columns of the memory device comprises:
a first plurality of memory cells;
a first pair of bit lines connected to each of the first plurality of bit cells; and
a second pair of bit lines connectable to the first pair of bit lines through a plurality of pair of switches, wherein a first pair of switches of the plurality of pair of switches is connected between the first pair of bit lines and the second pair of bit lines, wherein a second pair of switches of the plurality of pair of switches is connected between the first pair of bit lines and the second pair of bit lines after a first predetermined number of rows of a plurality of rows of a cell array of the memory device from the first pair of switches, wherein the plurality of pair of switches remain switched off thereby disconnecting the second pair of bit lines from the first pair of bit lines during a read operation in the memory device, and wherein the plurality of pair of switches are switched on thereby connecting the second pair of bit lines to the first pair of bit lines during a write operation in the memory device through the plurality of pair of switches.