US 12,260,903 B2
Memory devices with improved bit line loading
Yi-Hsin Nien, Hsinchu (TW); Hidehiro Fujiwara, Hsinchu (TW); Chih-Yu Lin, Taichung (TW); and Yen-Huei Chen, Jhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 12, 2022, as Appl. No. 17/863,092.
Prior Publication US 2024/0021240 A1, Jan. 18, 2024
Int. Cl. G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 27/02 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H01L 27/0207 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory array, comprising:
a plurality of memory cells disposed over a substrate,
wherein each of the plurality of memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs,
wherein first four memory cells of the plurality of memory cells that are coupled to four consecutive ones of the plurality of word lines are abutted to one another on the substrate along a single lateral direction,
wherein two of the first four memory cells are operatively coupled to a first one of the plurality of bit line pairs and other two of the first four memory cells are operatively coupled to a second one of the plurality of bit line pairs, and
wherein the first one of the plurality of bit line pairs and the second one of the plurality of bit line pairs correspond to one of a plurality of columns.