US 12,260,902 B2
Complementary storage unit and method of preparing the same, and complementary memory
Qing Luo, Beijing (CN); Bing Chen, Beijing (CN); Hangbing Lv, Beijing (CN); Ming Liu, Beijing (CN); and Cheng Lu, Beijing (CN)
Assigned to Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
Appl. No. 18/042,574
Filed by Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
PCT Filed Aug. 24, 2020, PCT No. PCT/CN2020/110791
§ 371(c)(1), (2) Date Feb. 22, 2023,
PCT Pub. No. WO2022/040859, PCT Pub. Date Mar. 3, 2022.
Prior Publication US 2023/0335182 A1, Oct. 19, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); H03K 19/017 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); H03K 19/01742 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A complementary storage unit, comprising:
a control transistor configured to control reading and writing of the storage unit;
a pull-up diode, wherein one end of the pull-up diode is connected to a positive selection line, and the other end of the pull-up diode is connected to a source end of the control transistor, so as to control a high-level input; and
a pull-down diode, wherein one end of the pull-down diode is connected to a negative selection line, and the other end of the pull-down diode is connected to the source end of the control transistor, so as to control a low-level input;
wherein the pull-up diode and the pull-down diode are symmetrically arranged in a first direction.