| CPC G11C 11/4093 (2013.01) [G11C 5/063 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2254 (2013.01)] | 16 Claims |
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1. A signal input buffer comprising:
1-st and 2-nd buffering blocks, each of the 1-st and 2-nd buffering blocks buffering its own input signal pair to generate its own output signal pair, and calibrating its own calibration code in a 1-st calibration period and a 2-nd calibration period, respectively, wherein the input signal pair includes an intrinsic input signal and a complementary input signal, and the output signal pair includes an intrinsic output signal and a complementary output signal;
a 1-st input switching block that electrically connects a reception signal pair to the input signal pair of the 1-st buffering block in the 2-nd calibration period, and blocks electrical connection between the reception signal pair and the input signal pair of the 1-st buffering block in the 1-st calibration period;
a 2-nd input switching block that electrically connects the reception signal pair to the input signal pair of the 2-nd buffering block in the 1-st calibration period, and blocks electrical connection between the reception signal pair and the input signal pair of the 2-nd buffering block in the 2-nd calibration period;
a 1-st output switching block that electrically connects the output signal pair of the 1-st buffering block to a buffered signal pair in the 2-nd calibration period, and blocks electrical connection between the output signal pair of the 1-st buffering block and the buffered signal pair in the 1-st calibration period; and
a 2-nd output switching block that electrically connects the output signal pair of the 2-nd buffering block to the buffered signal pair in the 1-st calibration period, and blocks electrical connection between the output signal pair of the 2-nd buffering block and the buffered signal pair in the 2-nd calibration period, wherein
the signal input buffer buffers the reception signal pair and generates the buffered signal pair, and is capable of operation in a normal mode and a calibration mode,
the reception signal pair includes an intrinsic reception signal and a complementary reception signal,
the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal,
the calibration mode includes the 1-st calibration period and the 2-nd calibration period,
the k-th input switching block electrically connects the reception signal pair to the input signal pair of the k-th buffering block in the normal mode, ‘k’ being at least one of 1 and 2,
the k-th output switching block electrically connects the output signal pair of the k-th buffering block to the buffered signal in the normal mode,
the k-th buffering block includes:
a switching circuit that controls the intrinsic input signal and the complementary input signal to a same voltage level in the k-th calibration period;
a reception circuit that includes a reception response unit and a comparison response unit, and generates the output signal pair, wherein the reception response unit has a reception response conductance which depends on a voltage of the intrinsic input signal, the comparison response unit has a comparison response conductance which depends on a voltage of the complementary input signal, and the output signal pair has a logic state depending on a magnitude relationship between the reception response conductance and the comparison response conductance in the k-th calibration period; and
a code generating circuit that generates a calibration code including 1-st to n-th calibration signals sequentially activated, wherein the calibration code is sequentially changed in k-th the calibration period in which a k-th calibration driving signal is activated, and is latched in response to a transition of the intrinsic output signal,
a relative magnitude of the comparison response conductance to the reception response conductance is sequentially changed according to the sequential change of the calibration code, in the k-th calibration period, and
‘k’ is at least one of 1 and 2, and ‘n’ is a natural number equal to greater than 2.
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