US 12,260,899 B2
Decoder driver circuit and memory chip
Weibing Shang, Hefei (CN); Xianjun Wu, Hefei (CN); and Minghao Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 17, 2023, as Appl. No. 18/155,079.
Application 18/155,079 is a continuation of application No. PCT/CN2022/108164, filed on Jul. 27, 2022.
Claims priority of application No. 202110981627.X (CN), filed on Aug. 25, 2021.
Prior Publication US 2023/0170011 A1, Jun. 1, 2023
Int. Cl. G11C 11/4074 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A decoder driver circuit, comprising:
a plurality of sub drive units configured to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal and an intermediate decoding output signal; and
a plurality of decoding control circuits connected to the plurality of sub drive units, the plurality of decoding control circuits being configured to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal;
wherein when the intermediate decoding output signal is in a first state, the main word line drive signal is in a non-drive state; and,
wherein each of the plurality of sub drive units comprises:
a first transistor, a source of the first transistor being connected to the power supply voltage signal, a gate of the first transistor being connected to the first decoding input signal;
a second transistor, a source of the second transistor being connected to the power supply voltage signal, a gate of the second transistor being connected to the intermediate decoding output signal; and
a third transistor, a source of the third transistor being connected to a given one of the plurality of decoding control circuits, a drain of the third transistor being connected to both a drain of the first transistor and a drain of the second transistor, and a gate of the third transistor being connected to both the gate of the first transistor and the first decoding input signal; and
the enable control signal comprises a first enable control signal and a second enable control signal, the given decoding control circuit comprising:
a first inverter, a power supply terminal of the first inverter being connected to a first power supply, an output terminal of the first inverter being connected to the gate of the second transistor;
a fourth transistor, a source of the fourth transistor being grounded, a drain of the fourth transistor being connected to the source of the third transistor, and a gate of the fourth transistor being connected to both the gate of the second transistor and the output terminal of the first inverter;
a fifth transistor, a source of the fifth transistor being connected to the first power supply, a drain of the fifth transistor being connected to an input terminal of the first inverter, and a gate of the fifth transistor being connected to both the output terminal of the first inverter and the gate of the second transistor;
a sixth transistor, a source of the sixth transistor being connected to the first power supply, a drain of the sixth transistor being connected to both the input terminal of the first inverter and the drain of the fifth transistor, and a gate of the sixth transistor being connected to the first enable control signal; and
a seventh transistor, a source of the seventh transistor being connected to a second decoding signal receiver unit, a drain of the seventh transistor being connected to both the drain of the sixth transistor and the input terminal of the first inverter, and a gate of the seventh transistor being connected to the second enable control signal.