US 12,260,898 B2
Memory device and electronic device
Shunpei Yamazaki, Tokyo (JP); Kiyoshi Kato, Kanagawa (JP); Takahiko Ishizu, Kanagawa (JP); and Tatsuya Onuki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on May 7, 2024, as Appl. No. 18/657,376.
Application 18/657,376 is a continuation of application No. 18/206,117, filed on Jun. 6, 2023, granted, now 11,984,152.
Application 18/206,117 is a continuation of application No. 17/849,894, filed on Jun. 27, 2022, granted, now 11,705,184, issued on Jul. 18, 2023.
Application 17/849,894 is a continuation of application No. 17/041,037, granted, now 11,404,107, issued on Aug. 2, 2022, previously published as PCT/IB2019/052244, filed on Mar. 20, 2019.
Claims priority of application No. 2018-065571 (JP), filed on Mar. 29, 2018; and application No. 2018-169247 (JP), filed on Sep. 10, 2018.
Prior Publication US 2024/0304231 A1, Sep. 12, 2024
Int. Cl. G11C 11/24 (2006.01); G11C 11/408 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H10B 99/00 (2023.01)
CPC G11C 11/4085 (2013.01) [H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H10B 99/00 (2023.02)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a transistor, the semiconductor device comprising:
a first conductive film comprising a region being a first gate of the transistor;
a first insulating film over the first conductive film;
an oxide semiconductor film over the first insulating film;
a second insulating film over the oxide semiconductor film;
a second conductive film comprising a region being a second gate electrode of the transistor, over the second insulating film;
a third insulating film over the second conductive film;
a third conductive film in contact with an upper surface of the third insulating film; and
a fourth conductive film in contact with the upper surface of the third insulating film,
wherein the oxide semiconductor film comprises a channel formation region of the transistor,
wherein the third conductive film is electrically connected to the oxide semiconductor film,
wherein the fourth conductive film is electrically connected to the first conductive film,
wherein the first conductive film and the second conductive film each comprises a region extending along a first direction,
wherein the first conductive film comprises a first width in a second direction intersecting with the first direction,
wherein the fourth conductive film comprises a second width in the second direction, and
wherein the first width is smaller than the second width.