US 12,260,897 B2
Separated read BL scheme in 3T dram for read speed improvement
Hidehiro Fujiwara, Hsin-chu (TW); Yi-Hsun Chiu, Zhubei (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/870,208.
Application 17/870,208 is a division of application No. 17/085,287, filed on Oct. 30, 2020, granted, now 11,482,276.
Prior Publication US 2022/0358992 A1, Nov. 10, 2022
Int. Cl. G11C 11/408 (2006.01); G11C 11/4097 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4097 (2013.01); H10B 12/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory array comprising:
a plurality of memory cells arranged along a plurality of rows and a first column of a plurality of columns, wherein each of the plurality of rows extends in a row direction and each of the plurality of columns extends in a column direction that is perpendicular to the row direction;
a first interconnect layer defining a first read bit line in a layout design of the memory array, wherein the first interconnect layer is connected to a first set of the plurality of memory cells, and wherein the first set of the plurality of memory cells are arranged along a first set of the plurality of rows in the first column;
a second interconnect layer defining a second read bit line in the layout design, wherein the second interconnect layer is connected to a second set of the plurality of memory cells, and wherein the second set of the plurality of memory cells are arranged along a second set of the plurality of rows in the first column; and
a plurality of third interconnect layers extending in the row direction defining a plurality of read word lines in the layout design, wherein each of the plurality of read word lines is connected to one of the first set of the plurality of memory cells or one of the second set of the plurality of memory cells.