US 12,260,896 B2
Apparatus with memory process feedback
Sujeet Ayyapureddi, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 13, 2022, as Appl. No. 17/965,706.
Claims priority of provisional application 63/293,716, filed on Dec. 24, 2021.
Prior Publication US 2023/0206988 A1, Jun. 29, 2023
Int. Cl. G11C 11/4078 (2006.01); G11C 5/00 (2006.01); G11C 11/4096 (2006.01); G11C 29/52 (2006.01); G11C 7/24 (2006.01); G11C 8/08 (2006.01); G11C 29/04 (2006.01)
CPC G11C 11/4078 (2013.01) [G11C 5/005 (2013.01); G11C 11/4096 (2013.01); G11C 29/52 (2013.01); G11C 7/24 (2013.01); G11C 8/08 (2013.01); G11C 2029/0411 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory;
a controller coupled to the memory, the controller configured to:
monitor activity of at least one memory address in the memory;
identify the at least one memory address as a row hammer aggressor address when accesses thereto satisfy a predetermined condition;
inject at least one error into the identified at least one memory address; and
transmit a message to a host, wherein the message includes the identified at least one memory address in a process operating in the memory.