US 12,260,892 B2
Integrated circuit and memory device including sampling circuit
Jun Seok Noh, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 13, 2022, as Appl. No. 18/080,293.
Claims priority of application No. 10-2022-0111396 (KR), filed on Sep. 2, 2022.
Prior Publication US 2024/0079041 A1, Mar. 7, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/406 (2013.01) 24 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a sampling control circuit configured to:
generate a counting signal according to a periodic signal during a sampling period, and
generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal; and
a sampling circuit configured to:
store an input address as a plurality of sampling addresses according to the respective sampling enable signals, and
generate a plurality of valid section signals which are activated based on the respective sampling enable signals to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated valid section signals.