US 12,260,890 B2
Memory device which generates improved write voltage according to size of memory cell
Daeshik Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 19, 2023, as Appl. No. 18/545,626.
Application 18/545,626 is a division of application No. 17/399,264, filed on Aug. 11, 2021, granted, now 11,894,038.
Claims priority of application No. 10-2020-0101344 (KR), filed on Aug. 12, 2020.
Prior Publication US 2024/0119983 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An operating method of a memory device, the method comprising:
writing a memory device to a first state;
counting fail bits of the memory device that are programmed to the first state by using a first plurality of resistors having different values, the first plurality of resistors corresponding to each of a plurality of reference resistors;
writing the memory device to a second state;
counting fail bits of the memory device that are programmed to the second state by using the first plurality of resistors;
selecting a selected reference resistor from the first plurality of resistors based on (A) counting results associated with the first state and (B) counting results associated with the second state; and
determining a value of a write voltage for the memory device based on a value of the selected reference resistor.